1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a nonvolatile memory device capable of retaining data when electric power is cut off.
2. Description of the Related Art
Highly integrated, high-capacity nonvolatile memory devices have been rapidly developed to meet the increasing demand for portable storage devices. Examples of nonvolatile memory devices include programmable read only memories (PROMs), erasable and programmable read only memories (EPROMs), and electrically erasable and programmable read only memories (EEPROMs). Flash memories, a kind of EEPROM, are widely used.
A typical flash memory has a stacked structure including a tunneling insulation layer, a floating gate electrode, an inter-electrode insulation layer, and a control gate electrode that are formed on a semiconductor substrate. Cell characteristics of the flash memory vary depending on the thickness of the tunneling insulation layer, the contact area between the floating gate electrode and the semiconductor substrate, the contact area between the floating gate electrode and the control gate electrode, and/or the thickness of the inter-electrode insulation layer. Important characteristics of flash memory cells include programming speed, erasing speed, distribution of programming cells, and distribution of erasing cells. Characteristics of the flash memory cell, such as programming/erasing endurance and data retention characteristics, are related to the reliability of the flash memory.
In general, programming speed and erasing speed depend on the coupling ratio (γ) expressed by Equation 1 below. The coupling ratio (γ) is a ratio of a voltage induced at a floating gate electrode to a voltage applied to a control gate electrode. The coupling ratio (γ) depends on the capacitance Ctunnel of a tunneling insulation layer and the capacitance Cblock of an inter-electrode insulation layer.
                    γ        =                              C            block                                              C              tunnel                        +                          C              block                                                          [                  Equation          ⁢                                          ⁢          1                ]            
When the coupling ratio (γ) is high, high programming speed and erasing speed can be attained at a given operating voltage. Therefore, it is generally desirable to decrease the capacitance Ctunnel and/or to increase the capacitance Cblock.
Recent, highly integrated flash memories suffer from undesired coupling interference between neighboring floating gate electrodes due to the reduced design rule. The height of floating gate electrodes can be reduced to decrease mutually facing portions (overlapping portions) of neighboring floating gate electrodes, which reduces coupling interference between the neighboring floating gates. However, in this case, the capacitance Cblock of the inter-electrode insulation layer is reduced, thus reducing the coupling ratio (γ). This decreases the programming/erasing speed of a flash memory.